Modern semiconductor based integrated circuits (ICs) are incredibly complex and contain millions of circuit devices, such as transistors, and millions of interconnections between the circuit devices. Designing such complex circuits cannot be accomplished manually, and circuit designers use computer based Electronic Design Automation (EDA) tools for schematics, layouts, simulation, and verification of the complex circuits. EDA tools are also used in designing IC packages, the complexity of which has grown with the complexity of the IC designs.
An IC package generally provides housing for the semiconductor die that holds the integrated electronic circuit. The IC package further includes an interface array that contains a grid of pins or soldered balls to interface with the printed circuit board. The IC package also includes multiple and complex connections between the various input/output (IO) cells in the semiconductor die and the interface array for transmitting signals between the electronic circuit in the semiconductor die and the interface array. Such signals may include data signals and power provided to the electronic circuit. Furthermore, the IC package contains multiple discrete and embedded passive devices such as inductors, capacitors, and resistors for controlling the transmission of the signals and power in the connections between the semiconductor die and the interface array. In an IC package design, the various components such as the transmission lines, discrete devices, and embedded passive devices may be represented by parameterized/parameterizable/programmable cells, shortened as pcell (singular) or pcells (plural).
In an IC package with multiple routing layers, the transmission lines connecting the IO cells and the interface array have to be routed through multiple layers in the semiconductor die. Each of the layers of the semiconductor die has specific characteristics, for example the thickness of the metal, which governs the shape geometry of the transmission lines in the layer. In conventional EDA tools, a package designer has to create a unique library of transmission line layout cells for each layer, for instance by adapting pcells supplied by the EDA tools. For example, the library associated with a relatively higher layer will contain transmission line cells with a thicker geometry compared to the library associated with a relatively lower layer. It is cumbersome and inefficient to adapt pcells which are supplied by an EDA vendor to represent the multiple routing layers to suit the particular technology being used by the package designer.
It is similarly inefficient and cumbersome to adapt pcells supplied by an EDA vendor for the design layout of discrete and embedded passive components implemented within the routing layers of the IC design package. The discrete and embedded passive components within the IC design package, for example a discrete capacitor, have a layout footprint based upon the layer they are located. A package designer using conventional EDA tools captures the layout footprint of the discrete components prior to putting a package design together. When the layout footprint of the discrete components is so captured, the package designer does not have a way of knowing the layers that these discrete components will reside in. To get around this problem in the conventional EDA tools, the package designer has to define a library of the discrete components for each of the layers in the package by editing the pcells provided by the EDA tools/vendors, which is again cumbersome and inefficient.
What is therefore desired are automatically and intelligently customizable layout cells and electronic design automation (EDA) systems and methods implementing the customizable layout cells such that a package designer does not have to define a new cell library for every single routing layer of the package. In other words, what is required is a system library of layout cells such that the system library can be used seamlessly for future IC package layouts with yet unknown number of layers and the layout resolution of those unknown layers.